A crossbar switching matrix (CrossBar, Xbar) is a space division switch capable of connecting N input ports and N output ports to each other randomly, is also referred to as a cross switch matrix, and is used in a switching network.
As shown in FIG. 1, an Xbar includes a switching circuit and a switching matrix controller. The switching circuit is formed by vertically and horizontally cross-connected 2N links that connect N input ports (Input) and N output ports (Output). A control switch is provided at each crosspoint (Crosspoint) and is configured to control the connection between the Input and the Output. The switching matrix controller decides the connection relationship between the input port and the output port in each scheduling period according to the state of an input queue. An arbitration mechanism arbitrates access of the input port to the output port, and the switching matrix controller enables or disables the relevant crosspoint according to an arbitration result, so as to realize data switching.
As shown in FIG. 2, a switching system includes a switching network (Switching, SW) and a switching port, the switching network includes a crossbar switching matrix, and the switching port is specifically a switching network interface chip (Fabric Access Processor, FAP). A switching matrix controller of the crossbar switching matrix generates arbitration result (grant) information according to the state of an input queue, and sends the grant information to the switching port. The switching port sends, according to the grant information, a cell (cell) to the switching network for switching.
Due to a delay on a link, a long time may elapse after the SW sends the grant and before the SW receives the cell. Moreover, because different links have different delays, cells corresponding to grants sent by the SW at the same time arrive at different time. The period of time from sending the grant to finally completing switching of the cell by the SW is called Grant to Switch (G2S). The G2S time depends on the maximum link delay. In addition, due to a jitter on the link, the delay of the cell even on the same link varies. To ensure simultaneous switching, the link delay and the jitter delay need to be additionally processed before the switching.
In the prior art, a cell buffer is used to compensate for the link delay and jitter delay: after a cell on a fast link arrives, the cell waits in the buffer until a cell on the slowest link arrives, and then the cells are switched together. The specific solution is as follows: The SW sends a timestamp syncts to the FAP module while sending a grant. The timestamp syncts indicates a switching time of a corresponding cell. The FAP module sends the syncts as a field in a cell header together with the cell. A buffer is set in the SW for each input port, the buffer includes multiple units, and each unit corresponds to a value of syncts. After receiving the cell, the SW stores the cell in the corresponding buffering unit according to the syncts in the cell header. When the switching time indicated by the syncts arrives, the switching matrix controller loads switched configuration (namely, an arbitration result) corresponding to the syncts into the switching circuit, and meanwhile each input port reads the cell corresponding to the syncts from the buffer, so that the switched configuration is consistent with the switched cell, and finally, cell switching is completed. Detailed description is provided below with reference to an accompanying drawing.
In an Xbar shown FIG. 3, a buffer cbuf is used before a switching circuit to store a cell to be switched to absorb the jitter delay and link delay on a link. The buffer cbuf has a total of N×M units, respectively corresponding to N input links and M switching time, where M cannot be smaller than the value of G2S. Meanwhile, the value range of a syncts field carried in a cell header also cannot be smaller than the value of G2S, so as to realize mapping between syncts values and buffering units. The Xbar further includes a buffer ctbl which needs to buffer M arbitration results (namely, switched configuration). At each time of switching, an SW sends switched configuration corresponding to current syncts from the buffer ctbl to the switching circuit, and meanwhile sends all input cells corresponding to the current syncts from the buffer cbuf to the switching circuit. At the switching time, because grant information of this group of cells is sent before the G2S time, and the maximum link delay does not exceed G2S, the cells in all links corresponding to the syncts have been received in the buffer at the switching time, so that the link jitter is absorbed and the delay is corrected.
During the research and practice of the prior art, the inventors of the present invention find that, the syncts field in the cell header occupies some bits, which reduces the payload of the cell; in addition, the number of buffering units required by each input port of the SW cannot be smaller than the maximum syncts value, while the syncts value depends on the value of G2S and cannot be smaller than the value of G2S. The prior art lacks a technical solution by using which the payload of the cell is increased and the size of the cell buffer is reduced.